1. Field of the Invention
This invention generally relates to a semiconductor device, and, in particular, to a sense circuit of a semiconductor memory device for sensing the data written in the memory device to be either "1" or "0."
2. Description of the Prior Art
A typical prior art sense circuit comprised of an N-channel MOS transistor is shown in FIG. 2. As shown, the sense circuit includes a bit line connected to a memory cell 4. The bit line 2 is connected to a voltage source V.sub.cc through a MOS transistor 6 for supplying current to the memory cell 4. Also provided is a MOS transistor 8 for detecting the potential of the bit line, and the MOS transistor 8 has its gate connected to the bit line 2, its source connected to a ground terminal, and its drain connected to the supply voltage V.sub.cc through a depletion-type MOS transistor 10 serving as a load. The MOS transistors 6 and 10 have their gates connected to a node 11 which is a junction between the MOS transistors 8 and 10, and the node 11 defines an output of the sense circuit and is connected to an amplifier 12.
In this prior art sense circuit, the voltage at the bit line 2 is detected by a voltage difference V.sub.gs between the gate and the source of the MOS transistor 8. And, if the ground potential fluctuates due to noises from inside and outside of the semiconductor device, an erroneous operation in detecting the voltage at the bit line 2 or reading of the memory cell 4 would result. And, if a noise margin is to be provided for such fluctuations of the ground level, there is produced a reduction in the operational speed as a memory speed, such as data read out speed, so that the overall performance of the memory device would deteriorate.